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(parent: f47b490) | patch
tools/litex_sim: fix default endianness for mem_init
authorGabriel L. Somlo <gsomlo@gmail.com>
Tue, 18 Jun 2019 20:29:23 +0000 (16:29 -0400)
committerGabriel L. Somlo <gsomlo@gmail.com>
Tue, 18 Jun 2019 20:55:58 +0000 (16:55 -0400)
commitab827d210d302789db5ae6815aed70989ca43a1b
tree7acbe9bbc846f1547e7a4f2d3a1c252db5a799b7tree
parentf47b4902e53dc2ee66924449dcbedd4a09e07589commit | diff
tools/litex_sim: fix default endianness for mem_init

Initializing ROM and/or RAM content requires knowing the CPU
endianness before the SimSoC->SoCSDRAM->SoCCore constructor
sequence is invoked (before the SoC's self.cpu.endianness
could be accessed). Given that the majority of supported CPU
models use "little", set it as the new default, and override
only for the two models that use "big" endianness.
litex/tools/litex_sim.py diff | blob | history