add first subvl unit test, subvl comes from
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 20 Jul 2022 18:35:24 +0000 (19:35 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 20 Jul 2022 18:35:24 +0000 (19:35 +0100)
commitac4d2c60a9f428e90e6d7907707f47c915c3ce6f
tree0606415bcab765bfc2de447a43d5c653fa17e921
parentcca75a0619c9d6a8fb657608fbaf29e3dbdd6a91
add first subvl unit test, subvl comes from
RM not SVSTATE
src/openpower/decoder/isa/caller.py
src/openpower/decoder/isa/test_caller_svp64_subvl.py [new file with mode: 0644]
src/openpower/decoder/power_decoder2.py