mem: Reorganize cache tags and make them a SimObject
authorPrakash Ramrakhyani <prakash.ramrakhyani@arm.com>
Thu, 27 Jun 2013 09:49:50 +0000 (05:49 -0400)
committerPrakash Ramrakhyani <prakash.ramrakhyani@arm.com>
Thu, 27 Jun 2013 09:49:50 +0000 (05:49 -0400)
commitac515d7a9b131ffc9e128bd209fcddb2f383808b
tree4a445dffeed869dac321abc09b04d7c3d65601fe
parent0d68d36b9d12c36e6201fa8bc4bec34258c04eab
mem: Reorganize cache tags and make them a SimObject

This patch reorganizes the cache tags to allow more flexibility to
implement new replacement policies. The base tags class is now a
clocked object so that derived classes can use a clock if they need
one. Also having deriving from SimObject allows specialized Tag
classes to be swapped in/out in .py files.

The cache set is now templatized to allow it to contain customized
cache blocks with additional informaiton. This involved moving code to
the .hh file and removing cacheset.cc.

The statistics belonging to the cache tags are now including ".tags"
in their name. Hence, the stats need an update to reflect the change
in naming.
14 files changed:
src/mem/cache/BaseCache.py
src/mem/cache/base.cc
src/mem/cache/cache.hh
src/mem/cache/cache_impl.hh
src/mem/cache/tags/SConscript
src/mem/cache/tags/Tags.py [new file with mode: 0644]
src/mem/cache/tags/base.cc
src/mem/cache/tags/base.hh
src/mem/cache/tags/cacheset.cc [deleted file]
src/mem/cache/tags/cacheset.hh
src/mem/cache/tags/fa_lru.cc
src/mem/cache/tags/fa_lru.hh
src/mem/cache/tags/lru.cc
src/mem/cache/tags/lru.hh