arch-riscv: fix MIE csr register setting bugs
authorCui Jin <cuijin7@huawei.com>
Tue, 22 Dec 2020 08:46:46 +0000 (16:46 +0800)
committerCui Jin <cuijin7@huawei.com>
Thu, 31 Dec 2020 03:17:09 +0000 (03:17 +0000)
commitacfb233685a69078ef9c04829815436b687beae8
treefaaca524ef246d8ddac248e2d05825c57e2cd999
parent400152d5cb41a7a60b16fd64fd832cbc9f564205
arch-riscv: fix MIE csr register setting bugs

Any changes on xIE bits changes should trigger the updating
of CSR register. The old condition is wrongly reversed.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-855

Change-Id: Ia2c6d3fbfd24d7f9d23f7cfa6f25f893544f4157
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38578
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/riscv/isa/formats/standard.isa