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(parent: ae38fd4) | patch
soc_sdram: Don't add the L2 Cache when there's no wishbone bus
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 23 Sep 2019 13:53:07 +0000 (15:53 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Mon, 23 Sep 2019 13:53:07 +0000 (15:53 +0200)
commitad8830d9778a4285bc0dd4992f0522affade2051
tree8565d4ebb0b00f8196b05dbe90e8154ca5378ac2tree
parentae38fd424449ba5dabc738a69d0baf2d7b58e507commit | diff
soc_sdram: Don't add the L2 Cache when there's no wishbone bus
litex/soc/integration/soc_core.py diff | blob | history
litex/soc/integration/soc_sdram.py diff | blob | history