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(parent: cf67e6a) | patch
generate only simple assignments in verilog backend
authorMiodrag Milanovic <mmicko@gmail.com>
Wed, 25 Nov 2020 16:43:28 +0000 (17:43 +0100)
committerMiodrag Milanovic <mmicko@gmail.com>
Wed, 25 Nov 2020 16:43:28 +0000 (17:43 +0100)
commitaddc493e8d7f64267661af3bf7fbaf265e2b17ba
tree6eb04bf55fea7f68af8fef8c7803d41ba31f3d9btree
parentcf67e6a3977410e039d62a1e9f6c49c42cb97b08commit | diff
generate only simple assignments in verilog backend
backends/verilog/verilog_backend.cc diff | blob | history