arch: Make a base class for Interrupts.
authorGabe Black <gabeblack@google.com>
Tue, 3 Sep 2019 04:26:12 +0000 (21:26 -0700)
committerGabe Black <gabeblack@google.com>
Sat, 19 Oct 2019 01:45:48 +0000 (01:45 +0000)
commitae390c629f2a10fd6a1c2eb50b7d3510d6e091da
tree51f12635838755ef7519bea1c72bfb96e0214336
parent1c047f8b92f5708bbef50d24cf47902d5da313e3
arch: Make a base class for Interrupts.

That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.

Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
31 files changed:
src/arch/alpha/AlphaInterrupts.py
src/arch/alpha/interrupts.hh
src/arch/alpha/isa/decoder.isa
src/arch/arm/ArmInterrupts.py
src/arch/arm/interrupts.hh
src/arch/arm/isa.cc
src/arch/arm/isa/includes.isa
src/arch/arm/isa/insts/misc.isa
src/arch/generic/BaseInterrupts.py [new file with mode: 0644]
src/arch/generic/SConscript
src/arch/generic/interrupts.hh [new file with mode: 0644]
src/arch/mips/MipsInterrupts.py
src/arch/mips/interrupts.cc
src/arch/mips/interrupts.hh
src/arch/power/PowerInterrupts.py
src/arch/power/interrupts.hh
src/arch/riscv/RiscvInterrupts.py
src/arch/riscv/interrupts.hh
src/arch/riscv/isa.cc
src/arch/sparc/SparcInterrupts.py
src/arch/sparc/interrupts.hh
src/arch/sparc/isa.cc
src/arch/x86/X86LocalApic.py
src/arch/x86/interrupts.cc
src/arch/x86/interrupts.hh
src/arch/x86/pagetable_walker.cc
src/cpu/BaseCPU.py
src/cpu/base.hh
src/cpu/kvm/base.hh
src/cpu/kvm/x86_cpu.cc
src/dev/x86/i82094aa.cc