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(parent: 7d6cee6) | patch
litex/gen: reintegrate migen with modifications to be able to simulate with vpi until...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Thu, 12 Nov 2015 19:06:59 +0000 (20:06 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 13 Nov 2015 13:44:16 +0000 (14:44 +0100)
commitae3d54499aac40a08bfa7b2511733d3003391b42
tree974c9c3dacbaa0da96c9389082e43982e4147a39tree
parent7d6cee6751a4349cebe2bda6053417b25b5e59bdcommit | diff
litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented
39 files changed:
litex/gen/MIGEN_LICENSE [new file with mode: 0644] blob
litex/gen/__init__.py diff | blob | history
litex/gen/fhdl/__init__.py [new file with mode: 0644] blob
litex/gen/fhdl/bitcontainer.py [new file with mode: 0644] blob
litex/gen/fhdl/conv_output.py [new file with mode: 0644] blob
litex/gen/fhdl/decorators.py [new file with mode: 0644] blob
litex/gen/fhdl/edif.py [new file with mode: 0644] blob
litex/gen/fhdl/module.py [new file with mode: 0644] blob
litex/gen/fhdl/namer.py [new file with mode: 0644] blob
litex/gen/fhdl/simplify.py [new file with mode: 0644] blob
litex/gen/fhdl/specials.py [new file with mode: 0644] blob
litex/gen/fhdl/structure.py [new file with mode: 0644] blob
litex/gen/fhdl/tools.py [new file with mode: 0644] blob
litex/gen/fhdl/tracer.py [new file with mode: 0644] blob
litex/gen/fhdl/verilog.py [new file with mode: 0644] blob
litex/gen/fhdl/visit.py [new file with mode: 0644] blob
litex/gen/genlib/__init__.py [new file with mode: 0644] blob
litex/gen/genlib/cdc.py [new file with mode: 0644] blob
litex/gen/genlib/coding.py [new file with mode: 0644] blob
litex/gen/genlib/divider.py [new file with mode: 0644] blob
litex/gen/genlib/fifo.py [new file with mode: 0644] blob
litex/gen/genlib/fsm.py [new file with mode: 0644] blob
litex/gen/genlib/io.py [new file with mode: 0644] blob
litex/gen/genlib/misc.py [new file with mode: 0644] blob
litex/gen/genlib/record.py [new file with mode: 0644] blob
litex/gen/genlib/resetsync.py [new file with mode: 0644] blob
litex/gen/genlib/roundrobin.py [new file with mode: 0644] blob
litex/gen/genlib/sort.py [new file with mode: 0644] blob
litex/gen/sim/__init__.py [new file with mode: 0644] blob
litex/gen/sim/generic.py [new file with mode: 0644] blob
litex/gen/sim/icarus.py [new file with mode: 0644] blob
litex/gen/sim/ipc.py [new file with mode: 0644] blob
litex/gen/sim/upper.py [new file with mode: 0644] blob
litex/gen/util/__init__.py [new file with mode: 0644] blob
litex/gen/util/misc.py [new file with mode: 0644] blob
litex/gen/vpi/Makefile [new file with mode: 0644] blob
litex/gen/vpi/ipc.c [new file with mode: 0644] blob
litex/gen/vpi/ipc.h [new file with mode: 0644] blob
litex/gen/vpi/main.c [new file with mode: 0644] blob