back.rtlil: do not emit $next wires for comb signals.

back.rtlil: do not emit $next wires for comb signals.

According to RTLIL semantics (that was undocumented before today),
the only purpose of `sync always` is to enable inference of latches,
because there is no other way to express them in terms of RTLIL
processes without ending up with a combinatorial loop. But, nMigen
specifically avoids latches, so this is not necessary.

This change results in major improvements in Verilog readability.

See also #98.