mmu: Take an extra cycle to do TLB invalidations
authorPaul Mackerras <paulus@ozlabs.org>
Sat, 13 Jun 2020 10:27:50 +0000 (20:27 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Sat, 13 Jun 2020 10:27:50 +0000 (20:27 +1000)
commitaebd915f8f465f66f33703164f9fdec419a53aa6
tree9be42fb6930b4759f33cf13b79240b78edde91db
parentb5959632332cefbcb12537580710ba706fc79cf5
mmu: Take an extra cycle to do TLB invalidations

This makes the TLB invalidations that occur as a result of a tlbie,
slbia or mtspr instruction take one more cycle.  This breaks some
long combinatorial chains from decode2 to dcache and icache and
thus eases timing.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
mmu.vhdl