git.libre-soc.org Git - yosys.git/commit

author	Marcelina Kościelnicka <mwk@0x04.net>
	Mon, 18 May 2020 16:15:03 +0000 (18:15 +0200)
committer	Marcelina Kościelnicka <mwk@0x04.net>
	Mon, 18 May 2020 23:42:40 +0000 (01:42 +0200)
commit	aee439360bba642dcbffe5b803aa9a994b11d183
tree	a5c15b4a6172ea3ff651f88174fff7d5269ad1c2	tree
parent	2d573a0ff680eb9f38358943fbf134f765ba1451	commit \| diff

Add force_downto and force_upto wire attributes.

Fixes #2058.

43 files changed:

frontends/ast/genrtlil.cc		diff \| blob \| history
frontends/ast/simplify.cc		diff \| blob \| history
kernel/constids.inc		diff \| blob \| history
techlibs/achronix/speedster22i/cells_arith.v		diff \| blob \| history
techlibs/achronix/speedster22i/cells_map.v		diff \| blob \| history
techlibs/anlogic/arith_map.v		diff \| blob \| history
techlibs/anlogic/cells_map.v		diff \| blob \| history
techlibs/common/adff2dff.v		diff \| blob \| history
techlibs/common/cmp2lcu.v		diff \| blob \| history
techlibs/common/cmp2lut.v		diff \| blob \| history
techlibs/common/dff2ff.v		diff \| blob \| history
techlibs/common/mul2dsp.v		diff \| blob \| history
techlibs/common/techmap.v		diff \| blob \| history
techlibs/coolrunner2/cells_counter_map.v		diff \| blob \| history
techlibs/ecp5/arith_map.v		diff \| blob \| history
techlibs/ecp5/cells_map.v		diff \| blob \| history
techlibs/efinix/arith_map.v		diff \| blob \| history
techlibs/efinix/cells_map.v		diff \| blob \| history
techlibs/gowin/arith_map.v		diff \| blob \| history
techlibs/gowin/cells_map.v		diff \| blob \| history
techlibs/greenpak4/cells_map.v		diff \| blob \| history
techlibs/ice40/arith_map.v		diff \| blob \| history
techlibs/ice40/cells_map.v		diff \| blob \| history
techlibs/intel/arria10gx/cells_arith.v		diff \| blob \| history
techlibs/intel/arria10gx/cells_map.v		diff \| blob \| history
techlibs/intel/cyclone10lp/cells_arith.v		diff \| blob \| history
techlibs/intel/cyclone10lp/cells_map.v		diff \| blob \| history
techlibs/intel/cycloneiv/cells_arith.v		diff \| blob \| history
techlibs/intel/cycloneiv/cells_map.v		diff \| blob \| history
techlibs/intel/cycloneive/arith_map.v		diff \| blob \| history
techlibs/intel/cycloneive/cells_map.v		diff \| blob \| history
techlibs/intel/cyclonev/cells_arith.v		diff \| blob \| history
techlibs/intel/cyclonev/cells_map.v		diff \| blob \| history
techlibs/intel/max10/cells_arith.v		diff \| blob \| history
techlibs/intel/max10/cells_map.v		diff \| blob \| history
techlibs/intel_alm/common/alm_map.v		diff \| blob \| history
techlibs/intel_alm/common/arith_alm_map.v		diff \| blob \| history
techlibs/sf2/cells_map.v		diff \| blob \| history
techlibs/xilinx/arith_map.v		diff \| blob \| history
techlibs/xilinx/cells_map.v		diff \| blob \| history
techlibs/xilinx/lut_map.v		diff \| blob \| history
techlibs/xilinx/mux_map.v		diff \| blob \| history
tests/arch/xilinx/mux.ys		diff \| blob \| history

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