xilinx_dsp_cascade to also cascade AREG and BREG
authorEddie Hung <eddie@fpgeh.com>
Thu, 26 Sep 2019 20:29:18 +0000 (13:29 -0700)
committerEddie Hung <eddie@fpgeh.com>
Thu, 26 Sep 2019 20:29:18 +0000 (13:29 -0700)
commitaf59856ba1be1f7cde3154994334f45500af6c22
tree63ee305d8ddc997ecf726f9466fe979ad37ad8d7
parent832216dab072cb4f1793aeda07604fb2eb32b399
xilinx_dsp_cascade to also cascade AREG and BREG
passes/pmgen/xilinx_dsp.cc
passes/pmgen/xilinx_dsp_cascade.pmg