git.libre-soc.org Git - gem5.git/commit

author	Geoffrey Blake <geoffrey.blake@arm.com>
	Tue, 31 Jan 2012 15:46:03 +0000 (07:46 -0800)
committer	Geoffrey Blake <geoffrey.blake@arm.com>
	Tue, 31 Jan 2012 15:46:03 +0000 (07:46 -0800)
commit	af6aaf258171027af8d3cf0ef86dddff501a3ccb
tree	3473845b7217b48dcf43460f0a90ca655a7018ed	tree
parent	ade53def9252a36a39b2c4bd61196355906f0505	commit \| diff

CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5

Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU. These changes have only been tested with the ARM ISA. Other
ISAs potentially require modification.

38 files changed:

src/arch/arm/isa.cc		diff \| blob \| history
src/arch/arm/isa/insts/m5ops.isa		diff \| blob \| history
src/arch/arm/isa/insts/misc.isa		diff \| blob \| history
src/arch/arm/table_walker.cc		diff \| blob \| history
src/arch/arm/table_walker.hh		diff \| blob \| history
src/arch/arm/tlb.cc		diff \| blob \| history
src/arch/arm/tlb.hh		diff \| blob \| history
src/arch/arm/utility.cc		diff \| blob \| history
src/cpu/BaseCPU.py		diff \| blob \| history
src/cpu/CheckerCPU.py		diff \| blob \| history
src/cpu/DummyChecker.py	[new file with mode: 0644]	blob
src/cpu/SConscript		diff \| blob \| history
src/cpu/base.cc		diff \| blob \| history
src/cpu/base_dyn_inst.hh		diff \| blob \| history
src/cpu/base_dyn_inst_impl.hh		diff \| blob \| history
src/cpu/checker/cpu.cc		diff \| blob \| history
src/cpu/checker/cpu.hh		diff \| blob \| history
src/cpu/checker/cpu_impl.hh		diff \| blob \| history
src/cpu/checker/thread_context.hh		diff \| blob \| history
src/cpu/dummy_checker_builder.cc	[new file with mode: 0644]	blob
src/cpu/o3/O3CPU.py		diff \| blob \| history
src/cpu/o3/O3Checker.py		diff \| blob \| history
src/cpu/o3/checker_builder.cc		diff \| blob \| history
src/cpu/o3/commit_impl.hh		diff \| blob \| history
src/cpu/o3/cpu.cc		diff \| blob \| history
src/cpu/o3/cpu.hh		diff \| blob \| history
src/cpu/o3/dyn_inst_impl.hh		diff \| blob \| history
src/cpu/o3/fetch_impl.hh		diff \| blob \| history
src/cpu/o3/iew_impl.hh		diff \| blob \| history
src/cpu/o3/lsq_unit_impl.hh		diff \| blob \| history
src/cpu/o3/thread_context.hh		diff \| blob \| history
src/cpu/o3/thread_context_impl.hh		diff \| blob \| history
src/cpu/simple/BaseSimpleCPU.py		diff \| blob \| history
src/cpu/simple/base.cc		diff \| blob \| history
src/cpu/simple/base.hh		diff \| blob \| history
src/cpu/simple_thread.hh		diff \| blob \| history
src/cpu/thread_context.hh		diff \| blob \| history
src/mem/bus.cc		diff \| blob \| history

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