Provide debug access to SPRs in loadstore1 and mmu
authorPaul Mackerras <paulus@ozlabs.org>
Thu, 24 Feb 2022 00:37:17 +0000 (11:37 +1100)
committerPaul Mackerras <paulus@ozlabs.org>
Fri, 22 Jul 2022 12:20:45 +0000 (22:20 +1000)
commitaf814a0d5eedf433c52fc9674b1aa1241069f9be
tree8d423427301fcaf3a8c01207399aa76f831300b2
parentd0f319290fd22724a06b6db628aa7ee3458ca1bc
Provide debug access to SPRs in loadstore1 and mmu

They are accessible as GSPR 0x3c - PID, 0x3d - PTCR, 0x3e - DSISR
and 0x3f - DAR.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
common.vhdl
core.vhdl
core_debug.vhdl
loadstore1.vhdl
mmu.vhdl
scripts/mw_debug/mw_debug.c