xilinx_mult: Prepare for doing signed multiplication
authorPaul Mackerras <paulus@ozlabs.org>
Mon, 8 Aug 2022 07:06:46 +0000 (17:06 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Tue, 9 Aug 2022 10:17:03 +0000 (20:17 +1000)
commitaf9fe3467c91b46c053bdc81fcef45044ef09578
treebdc0aee4b5d9799c60fb477bee0a27cf8ffcef8d
parent595a7584008057a5be3b9a4a9bb1035ecccb23f9
xilinx_mult: Prepare for doing signed multiplication

This rearranges the way that partial products are generated and summed
so that the partial products that could be negative in a signed
multiplier are now sign-extended.  The inputs are still zero-extended,
however.

The overflow detection logic now only detects 64-bit overflow, since
32-bit multiplications are handled in a separate multiplier.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
xilinx-mult.vhdl