projects / yosys.git / commit
| author | Dan Ravensloft <dan.ravensloft@gmail.com> | |
| Sat, 25 Apr 2020 16:25:59 +0000 (17:25 +0100) | ||
| committer | Marcelina Kościelnicka <mwk@0x04.net> | |
| Sun, 5 Jul 2020 03:39:20 +0000 (05:39 +0200) | ||
| commit | b004f0901873962ba4a6fd3e12c7bc0cc1e04032 | |
| tree | 16d1bceb58a8b58690b5ba849173bfeef015bd4e | tree |
| parent | 01772dec8c13fb331df439319f4619b6292d6409 | commit | diff |
| techlibs/intel_alm/Makefile.inc | diff | blob | history | |
| techlibs/intel_alm/common/dsp_map.v | [new file with mode: 0644] | blob |
| techlibs/intel_alm/common/dsp_sim.v | [new file with mode: 0644] | blob |
| techlibs/intel_alm/common/megafunction_bb.v | diff | blob | history | |
| techlibs/intel_alm/common/quartus_rename.v | diff | blob | history | |
| techlibs/intel_alm/synth_intel_alm.cc | diff | blob | history | |
| tests/arch/intel_alm/mul.ys | [new file with mode: 0644] | blob |