MEM: Enable multiple distributed generalized memories
authorAndreas Hansson <andreas.hansson@arm.com>
Fri, 6 Apr 2012 17:46:31 +0000 (13:46 -0400)
committerAndreas Hansson <andreas.hansson@arm.com>
Fri, 6 Apr 2012 17:46:31 +0000 (13:46 -0400)
commitb00949d88bb3185dfa2e27799de7f90e5a449be8
tree74789b938463bcf38d5ffd5e6be5ef7a02d84a58
parentdbe1608fd58d818f59a0adf5f3fb562f61242f99
MEM: Enable multiple distributed generalized memories

This patch removes the assumption on having on single instance of
PhysicalMemory, and enables a distributed memory where the individual
memories in the system are each responsible for a single contiguous
address range.

All memories inherit from an AbstractMemory that encompasses the basic
behaviuor of a random access memory, and provides untimed access
methods. What was previously called PhysicalMemory is now
SimpleMemory, and a subclass of AbstractMemory. All future types of
memory controllers should inherit from AbstractMemory.

To enable e.g. the atomic CPU and RubyPort to access the now
distributed memory, the system has a wrapper class, called
PhysicalMemory that is aware of all the memories in the system and
their associated address ranges. This class thus acts as an
infinitely-fast bus and performs address decoding for these "shortcut"
accesses. Each memory can specify that it should not be part of the
global address map (used e.g. by the functional memories by some
testers). Moreover, each memory can be configured to be reported to
the OS configuration table, useful for populating ATAG structures, and
any potential ACPI tables.

Checkpointing support currently assumes that all memories have the
same size and organisation when creating and resuming from the
checkpoint. A future patch will enable a more flexible
re-organisation.

--HG--
rename : src/mem/PhysicalMemory.py => src/mem/AbstractMemory.py
rename : src/mem/PhysicalMemory.py => src/mem/SimpleMemory.py
rename : src/mem/physical.cc => src/mem/abstract_mem.cc
rename : src/mem/physical.hh => src/mem/abstract_mem.hh
rename : src/mem/physical.cc => src/mem/simple_mem.cc
rename : src/mem/physical.hh => src/mem/simple_mem.hh
65 files changed:
configs/common/FSConfig.py
configs/example/memtest.py
configs/example/ruby_direct_test.py
configs/example/ruby_mem_test.py
configs/example/ruby_network_test.py
configs/example/ruby_random_test.py
configs/example/se.py
configs/ruby/MESI_CMP_directory.py
configs/ruby/MI_example.py
configs/ruby/MOESI_CMP_directory.py
configs/ruby/MOESI_CMP_token.py
configs/ruby/MOESI_hammer.py
configs/ruby/Network_test.py
configs/ruby/Ruby.py
configs/splash2/cluster.py
configs/splash2/run.py
src/arch/alpha/remote_gdb.cc
src/arch/alpha/remote_gdb.hh
src/arch/arm/ArmSystem.py
src/arch/arm/linux/system.cc
src/arch/arm/remote_gdb.hh
src/arch/arm/system.cc
src/arch/mips/remote_gdb.hh
src/arch/sparc/SparcSystem.py
src/arch/sparc/remote_gdb.hh
src/base/remote_gdb.cc
src/base/remote_gdb.hh
src/cpu/checker/thread_context.hh
src/cpu/inorder/thread_context.hh
src/cpu/o3/fetch_impl.hh
src/cpu/ozone/cpu.hh
src/cpu/simple/atomic.cc
src/cpu/simple/atomic.hh
src/dev/alpha/backdoor.cc
src/dev/arm/RealView.py
src/dev/ide_disk.hh
src/mem/AbstractMemory.py [new file with mode: 0644]
src/mem/PhysicalMemory.py [deleted file]
src/mem/SConscript
src/mem/SimpleMemory.py [new file with mode: 0644]
src/mem/abstract_mem.cc [new file with mode: 0644]
src/mem/abstract_mem.hh [new file with mode: 0644]
src/mem/cache/mshr.cc
src/mem/physical.cc
src/mem/physical.hh
src/mem/ruby/system/RubyPort.cc
src/mem/simple_mem.cc [new file with mode: 0644]
src/mem/simple_mem.hh [new file with mode: 0644]
src/sim/System.py
src/sim/system.cc
src/sim/system.hh
tests/configs/inorder-timing.py
tests/configs/memtest-ruby.py
tests/configs/memtest.py
tests/configs/o3-timing-checker.py
tests/configs/o3-timing-mp.py
tests/configs/o3-timing.py
tests/configs/rubytest-ruby.py
tests/configs/simple-atomic-dummychecker.py
tests/configs/simple-atomic-mp.py
tests/configs/simple-atomic.py
tests/configs/simple-timing-mp-ruby.py
tests/configs/simple-timing-mp.py
tests/configs/simple-timing-ruby.py
tests/configs/simple-timing.py