projects / litex.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 68a5031) | patch
soc_core: use fixed 16MB CSR address space
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 10 Jul 2019 08:37:32 +0000 (10:37 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 10 Jul 2019 08:39:00 +0000 (10:39 +0200)
commitb0192e5f8bb6f1d97a2d023bbf9f947b77c19c8c
tree45bf59838190b0754f44b61cb2105b6f30870f94tree
parent68a503174cd02ca1e0a01b5a2e233ccd18643004commit | diff
soc_core: use fixed 16MB CSR address space

Using too small CSR address space cause a regression on PCIe SoC, this would
need to be understood if we want to reduce CSR address space under 16MB.
litex/soc/integration/soc_core.py diff | blob | history