projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 8d6e5c6) | patch
cxxrtl: expose port direction in debug information.
authorwhitequark <whitequark@whitequark.org>
Wed, 2 Sep 2020 15:18:44 +0000 (15:18 +0000)
committerwhitequark <whitequark@whitequark.org>
Wed, 2 Sep 2020 17:19:11 +0000 (17:19 +0000)
commitb025ee0aa646268747c121c97cf0673eb06e632b
tree2bcfbcc21c8cfc2c572418c79e43b99b5cfda83etree
parent8d6e5c63916bcff84164240cccce0e717e489a8dcommit | diff
cxxrtl: expose port direction in debug information.

This can be useful to distinguish e.g. a combinatorially driven wire
with type `CXXRTL_VALUE` from a module input with the same type, as
well as general introspection.
backends/cxxrtl/cxxrtl.h diff | blob | history
backends/cxxrtl/cxxrtl_backend.cc diff | blob | history
backends/cxxrtl/cxxrtl_capi.h diff | blob | history