arch-arm: ArmISA::clear, inval TLB cached miscregs

arch-arm: ArmISA::clear, inval TLB cached miscregs

ArmISA::clear resets the value of the architecture registers. Some of
these are cached in ArmTLB, including SCTLR. This patch invalidates the
cached copies on clear; this fixes a bug when resetting CPU cores by which
the cached SCTLR was used and SCTLR.M was set, resulting in non-arch
compliant reset behaviour and a PA being treated as a VA on translation.

Change-Id: I8d4eeeaf807325bd7b300a7a317abfa40ad23c87
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25466
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>