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(parent: 0aa3c33) | patch
gen/fhdl/verilog: explicitly define input/output/inout wires.
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 5 May 2020 14:58:33 +0000 (16:58 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 5 May 2020 14:58:33 +0000 (16:58 +0200)
commitb0578580714ad7d298e244fc3835c06ba082f2c1
tree4d5e4a917cf7a6f6164b7561d9458437d0ecc335tree
parent0aa3c339ccfddad71657060448c72a3144879311commit | diff
gen/fhdl/verilog: explicitly define input/output/inout wires.

When integrating designs which set `default_nettype none, the top also needs
to explicitly define the type of the signals.
litex/gen/fhdl/verilog.py diff | blob | history