Implement timer faithfully
authorAndrew Waterman <waterman@cs.berkeley.edu>
Mon, 1 Dec 2014 06:56:02 +0000 (22:56 -0800)
committerAndrew Waterman <waterman@cs.berkeley.edu>
Mon, 1 Dec 2014 06:56:02 +0000 (22:56 -0800)
commitb06c8e9f268badd23c12955a9c362c7842791429
tree7b639435b6658ba6c51b7eefd0d642580dc0ddc1
parent590417bec978bfc3fbf35d303760494395eb65b2
Implement timer faithfully

rdcycle/rdinstret now have single-instruction granularity.  Questionable
behavior when timer interrupts occurred around the same time as the compare
register is written should be fixed.
riscv/decode.h
riscv/insns/csrrc.h
riscv/insns/csrrci.h
riscv/insns/csrrs.h
riscv/insns/csrrsi.h
riscv/insns/csrrw.h
riscv/insns/csrrwi.h
riscv/processor.cc
riscv/processor.h
spike/spike.mk.in