hdl.ir: correctly handle named output and inout ports.
authorwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 04:03:03 +0000 (04:03 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 04:03:03 +0000 (04:03 +0000)
commitb0bd7bfaca2a549358b740d6325780b51fb7f26c
tree57e1a6979371660998ba3a38c0f4dbae7ebd0887
parent2b4a8510ca3653e796b0a6f8ac0d7868cfdf9a9b
hdl.ir: correctly handle named output and inout ports.
nmigen/hdl/ir.py
nmigen/test/test_hdl_ir.py