verilog: handle default in case statements
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Thu, 8 Dec 2011 22:04:20 +0000 (23:04 +0100)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Thu, 8 Dec 2011 22:04:20 +0000 (23:04 +0100)
commitb0c5b74c2284d1325d1dab1bed7492e9e03fb74c
tree4832569f3ecf2c8ae7210d9569a014d338b82a58
parent512655c108a072773fb910193261c03844300b08
verilog: handle default in case statements
migen/fhdl/verilog.py