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(parent: 9850de4) | patch
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
authorTim 'mithro' Ansell <me@mith.ro>
Mon, 8 Oct 2018 23:52:12 +0000 (16:52 -0700)
committerTim 'mithro' Ansell <me@mith.ro>
Mon, 8 Oct 2018 23:52:12 +0000 (16:52 -0700)
commitb111ea12286b45e51fc453e3f4d7ac906e1a9f7c
treead9fcd28339318054214e2503518be94b936d4d3tree
parent9850de405a11fe93e4562c86be0a0830b83c2785commit | diff
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.

Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
techlibs/xilinx/synth_xilinx.cc diff | blob | history