arch-arm: AArch64 trap check, arbitrary ECs/Imms
authorAdrian Herrera <adrian.herrera@arm.com>
Wed, 6 Nov 2019 13:30:15 +0000 (13:30 +0000)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Wed, 18 Dec 2019 09:14:08 +0000 (09:14 +0000)
commitb18c2e575ee079b873767b57604138e00bc1c465
treea00f7f5abcb66194266de22675c3bd5ec003be7f
parent3723cda9c2baa704602acaa8f941a996a636df49
arch-arm: AArch64 trap check, arbitrary ECs/Imms

This patch generalises trap checking when accessing system registers
in AArch64. Depending on the accessed register, a different Exception
Class (EC) and immediate value may be set.
Previously this only took SIMD traps into account.

Change-Id: I30717676a210c770531e39e4c6a6e1fbfdfdc583
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23765
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/insts/misc64.cc
src/arch/arm/insts/misc64.hh