[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.

[AArch64][PATCH 12/14] Support FP16 Adv.SIMD Scalar Pairwise instructions.

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Adv.SIMD Scalar Pairwise, making them
available when +simd+fp16 is enabled.

The instructions added are: FMAXNMP, FADDP, FMAXP, FMINNMP and FMINP

The general form for these instructions is
   <OP> <Hd>, <V>.<T>
   where T is 4h or 8h.

gas/testsuite/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD Scalar
	Pairwise instructions.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (QL_SISD_PAIR_H): New.
	(aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
	fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.

Change-Id: I19937ede3441b66dd0f940269ece895b17d3c345