sv: fix some edge cases for unbased unsized literals
authorZachary Snow <zach@zachjs.com>
Wed, 3 Mar 2021 19:36:19 +0000 (14:36 -0500)
committerZachary Snow <zachary.j.snow@gmail.com>
Sat, 6 Mar 2021 20:20:34 +0000 (15:20 -0500)
commitb1a8e73a609d3065f1caf7a230529443b54295bc
treee682f44ba07bf036005113e0dc5def403e8dc163
parentd245e2bae59d18eb641aa6b324eef1bbbfa13c38
sv: fix some edge cases for unbased unsized literals

- Fix explicit size cast of unbased unsized literals
- Fix unbased unsized literal bound directly to port
- Output `is_unsized` flag in `dumpAst`
frontends/ast/ast.cc
frontends/ast/simplify.cc
tests/verilog/unbased_unsized.sv [new file with mode: 0644]
tests/verilog/unbased_unsized.ys [new file with mode: 0644]