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(parent: 15e24b6) | patch
Revert "migen/fhdl/specials: use fdict to pass memory initialization files to Verilog...
authorSebastien Bourdeauducq <sb@m-labs.hk>
Mon, 30 Mar 2015 11:41:04 +0000 (19:41 +0800)
committerSebastien Bourdeauducq <sb@m-labs.hk>
Mon, 30 Mar 2015 11:41:04 +0000 (19:41 +0800)
commitb1c811a3d192deae7c1b14e1403cd40f0bd1f4ef
tree5b43cd32edb994e2ef18e2f79210b4eb108b5770tree
parent15e24b6c1061a317dafb59e471e93a6860a48901commit | diff
Revert "migen/fhdl/specials: use fdict to pass memory initialization files to VerilogConvert and print them in __str__ method"

This reverts commit 95cfc444e60ea18fa0efef229582923b2e695631.
migen/fhdl/specials.py diff | blob | history
migen/fhdl/verilog.py diff | blob | history