add testloop.s
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 21 May 2021 13:39:46 +0000 (14:39 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 21 May 2021 13:39:46 +0000 (14:39 +0100)
commitb211615f1b141935818e0e093b77eb6714b35578
tree29cdf93dd938e23bfb311f027b16cd5a7589bcd8
parent131570fb8e04b63f7d9c4a7c8869d9dbc87794d3
add testloop.s
src/test/basic_pypowersim/.gitignore [new file with mode: 0644]
src/test/basic_pypowersim/Makefile
src/test/basic_pypowersim/testloop.s [new file with mode: 0644]