projects / gem5.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 4056876) | patch
arch-riscv: fixed read of {M,S,U}TVEC.
authorNils Asmussen <nils.asmussen@barkhauseninstitut.org>
Thu, 13 Feb 2020 13:15:05 +0000 (14:15 +0100)
committerNils Asmussen <nils.asmussen@barkhauseninstitut.org>
Wed, 29 Apr 2020 11:41:55 +0000 (11:41 +0000)
commitb295e0f3a860349d420e3b6b5e7655a80dc54333
tree529aba944a65ceeb7d1fc2d47a7cf9f4fc61ab73tree
parent40568763016cbd09aa2e682575946e1bf04f2c73commit | diff
arch-riscv: fixed read of {M,S,U}TVEC.

As stated in 4.1.4 of the privileged ISA manual, the BASE field in the
STVEC register contains the bits [SXLEN-1:2] of the base address, not
the base address shifted left by 2.

Change-Id: I799ec0dc1cbd7b271b91b53adb033a5d1ca3306f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25648
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
src/arch/riscv/faults.cc diff | blob | history