sv: support declaration in generate for initialization
authorZachary Snow <zach@zachjs.com>
Tue, 31 Aug 2021 17:45:02 +0000 (11:45 -0600)
committerZachary Snow <zachary.j.snow@gmail.com>
Tue, 31 Aug 2021 18:34:55 +0000 (12:34 -0600)
commitb2e9717419e9a852f4e64f12891b8e9742900917
tree3a989a50c1f9beef9068b423f202d4918dcf3d6a
parentb20bb653ce0bfe452f8a1ff4a7a9b64262acced3
sv: support declaration in generate for initialization

This is accomplished by generating a unique name for the genvar,
renaming references to the genvar only in the loop's initialization,
guard, and incrementation, and finally adding a localparam inside the
loop body with the original name so that the genvar can be shadowed as
expected.
frontends/verilog/verilog_parser.y
tests/verilog/genfor_decl_no_init.ys [new file with mode: 0644]
tests/verilog/genfor_decl_no_sv.ys [new file with mode: 0644]
tests/verilog/genvar_loop_decl_1.sv [new file with mode: 0644]
tests/verilog/genvar_loop_decl_1.ys [new file with mode: 0644]
tests/verilog/genvar_loop_decl_2.sv [new file with mode: 0644]
tests/verilog/genvar_loop_decl_2.ys [new file with mode: 0644]
tests/verilog/genvar_loop_decl_3.sv [new file with mode: 0644]
tests/verilog/genvar_loop_decl_3.ys [new file with mode: 0644]