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(parent: d554e2b) | patch
Increase UART bridge speed in simulation, decrease simulation time
authorJean THOMAS <git0@pub.jeanthomas.me>
Wed, 15 Jul 2020 10:44:41 +0000 (12:44 +0200)
committerJean THOMAS <git0@pub.jeanthomas.me>
Wed, 15 Jul 2020 10:44:41 +0000 (12:44 +0200)
commitb3133e66c849eff228f98f1d306a6bf9dc12edb8
treedc314482a9ee2ff914ba56bdb02d148770493008tree
parentd554e2b8e5c5d209f0ab7e254127d565d5480ef6commit | diff
Increase UART bridge speed in simulation, decrease simulation time
gram/simulation/simsoc.py diff | blob | history
gram/simulation/simsoctb.v diff | blob | history