fix dsrd pseudocode for new 3-in 2-out
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 27 Oct 2022 14:47:53 +0000 (15:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 2 Jun 2023 18:51:15 +0000 (19:51 +0100)
commitb38b5537c70792eded9cf8dd02adce48355905d6
tree5c2082cfef9d6a7be1b06064be4b1dfded63d1cb
parentbbc5d2f7fbe47379f097569fd448911b87686203
fix dsrd pseudocode for new 3-in 2-out
https://bugs.libre-soc.org/show_bug.cgi?id=937#c16
openpower/isa/svfixedarith.mdwn
src/openpower/test/bigint/bigint_cases.py