Fix handling of empty cell port assignments (i.e. ignore them)
authorClifford Wolf <clifford@clifford.at>
Fri, 21 Jul 2017 17:32:31 +0000 (19:32 +0200)
committerClifford Wolf <clifford@clifford.at>
Fri, 21 Jul 2017 17:32:31 +0000 (19:32 +0200)
commitb3bc7068d1683cc0ac0b21cacdfb07867a7eeadb
tree6479759cc374b0306b812f90db1a754ff52f1ec6
parent36cf18ac4c1f96cad795032c3597abf08af6a6d8
Fix handling of empty cell port assignments (i.e. ignore them)
passes/hierarchy/hierarchy.cc
passes/techmap/techmap.cc