x86: Handle m5 op accesses directly in the mmapped IPR handlers.

x86: Handle m5 op accesses directly in the mmapped IPR handlers.

The common handlers only handle the m5ops, and it takes more plumbing
to get to them than to just handle the m5ops directly from x86.

Also, centralizing the call to PseudoInst::pseudoInst prevents
specializing the ABI per-ISA.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: Ife9cf0d61ac87605ddc9cf9c84feebb8b23cc33a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23184
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>