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(parent: f85286b) | patch
CPU: Moving towards a more general port across CPU models
authorAndreas Hansson <andreas.hansson@arm.com>
Tue, 17 Jan 2012 18:55:08 +0000 (12:55 -0600)
committerAndreas Hansson <andreas.hansson@arm.com>
Tue, 17 Jan 2012 18:55:08 +0000 (12:55 -0600)
commitb3f930c884ef23e4d784553fdccc91a772334fd7
treecafe3076cb93173cb0587e7f6c718efa178463e6tree
parentf85286b3debf4a4a94d3b959e5bb880be81bd692commit | diff
CPU: Moving towards a more general port across CPU models

This patch performs minimal changes to move the instruction and data
ports from specialised subclasses to the base CPU (to the largest
degree possible). Ultimately it servers to make the CPU(s) have a
well-defined interface to the memory sub-system.
18 files changed:
src/cpu/BaseCPU.py diff | blob | history
src/cpu/base.cc diff | blob | history
src/cpu/base.hh diff | blob | history
src/cpu/inorder/InOrderCPU.py diff | blob | history
src/cpu/o3/O3CPU.py diff | blob | history
src/cpu/o3/cpu.cc diff | blob | history
src/cpu/o3/cpu.hh diff | blob | history
src/cpu/o3/fetch.hh diff | blob | history
src/cpu/o3/fetch_impl.hh diff | blob | history
src/cpu/o3/iew.hh diff | blob | history
src/cpu/o3/lsq.hh diff | blob | history
src/cpu/o3/lsq_impl.hh diff | blob | history
src/cpu/simple/AtomicSimpleCPU.py diff | blob | history
src/cpu/simple/TimingSimpleCPU.py diff | blob | history
src/cpu/simple/atomic.cc diff | blob | history
src/cpu/simple/atomic.hh diff | blob | history
src/cpu/simple/timing.cc diff | blob | history
src/cpu/simple/timing.hh diff | blob | history