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(parent: 03b039a) | patch
RISC-V: Fix assembler for c.li, c.andi and c.addiw
authorKito Cheng <kito.cheng@gmail.com>
Tue, 7 Mar 2017 10:15:02 +0000 (18:15 +0800)
committerPalmer Dabbelt <palmer@dabbelt.com>
Wed, 15 Mar 2017 14:47:52 +0000 (07:47 -0700)
commitb416fe873ef44b2a613c9266c6462a481926d986
tree508c7f088305d110f17dd84951738a17314a7722tree
parent03b039a518fa0f89a9900a44a8b874cc91061305commit | diff
RISC-V: Fix assembler for c.li, c.andi and c.addiw

 - They can accept 0 in imm field

 2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

       * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
       <c.andi>: Likewise.
       <c.addiw> Likewise.
gas/ChangeLog diff | blob | history
gas/config/tc-riscv.c diff | blob | history
opcodes/ChangeLog diff | blob | history
opcodes/riscv-opc.c diff | blob | history