Wishbone debug module
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 10 Sep 2019 16:31:25 +0000 (17:31 +0100)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Fri, 20 Sep 2019 05:07:49 +0000 (15:07 +1000)
commitb46f81fae4c2700547ef791606fe20ed71c4fa81
treefe44ebde134ab1ab925f435e2ed36c0a07f3b7ad
parentee52fd4d809ef4c85424742387740e59825d8245
Wishbone debug module

This adds a debug module off the DMI (debug) bus which can act as a
wishbone master to generate read and write cycles.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Makefile
dmi_dtm_tb.vhdl
microwatt.core
scripts/mw_debug.py
soc.vhdl
wishbone_debug_master.vhdl [new file with mode: 0644]