Merge pull request #349 from madscientist159/master
authorMichael Neuling <mikey@neuling.org>
Fri, 25 Feb 2022 00:08:57 +0000 (11:08 +1100)
committerGitHub <noreply@github.com>
Fri, 25 Feb 2022 00:08:57 +0000 (11:08 +1100)
commitb4770197a2e07c321f283d8882a3dcb380a1344b
treedc1ffb49af47f5aef5f476311274e3b270a7c2f4
parent2b97fb0bf3d159a125122f8f0bdb5f24ef57e096
parentfcb783a0fb9b52fdffbc2ff49b8e6ceaaadbda3e
Merge pull request #349 from madscientist159/master

Extend LiteDRAM VHDL wrapper to allow more than one clock line