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(parent: 18b1ace) | patch
sim._pyrtl: reject very large values.
authorwhitequark <whitequark@whitequark.org>
Sat, 11 Dec 2021 13:00:46 +0000 (13:00 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 31 Dec 2021 20:18:49 +0000 (20:18 +0000)
commitb4b8c45dd7c255b178dd6a1c669b98dc14419f82
treea2724ce32c74b7934e073c38e6e911c823f7686ctree
parent18b1ace1855557bc69414dddd7554f6c3b5f9ed9commit | diff
sim._pyrtl: reject very large values.

A check that rejects very large wires already exists in back.rtlil
because they cause performance and correctness issues with Verilog
tooling. Similar performance issues exist with the Python simulator.

This commit also adjusts back.rtlil to use the OverflowError
exception, same as in sim._pyrtl.

Fixes #588.
nmigen/back/rtlil.py diff | blob | history
nmigen/sim/_pyrtl.py diff | blob | history
tests/test_sim.py diff | blob | history