cores/clock/S7: just reset the generated clock, not the PLL/MMCM
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 13 Nov 2018 13:46:20 +0000 (14:46 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 13 Nov 2018 13:47:04 +0000 (14:47 +0100)
commitb4bdf2a0233b1641316fe08ba30bb7d6fb12db01
tree263c7f69a321dfc91b76ef9cd5824723b03ebd13
parent86fd945bc3c30850f316d7a50705a2e04970fceb
cores/clock/S7: just reset the generated clock, not the PLL/MMCM
litex/soc/cores/clock.py