[libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
authorJacob Lifshay <programmerjake@gmail.com>
Wed, 13 May 2020 17:49:55 +0000 (10:49 -0700)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Wed, 13 May 2020 17:50:09 +0000 (18:50 +0100)
commitb4f13695d01f4d3c8ce72852a2cbda6f22be683c
tree0badf6321393b3531bf2b2ccc77abbe0036ffabf
parent6ed8317ef40287346d6edfc110ec3a5f39116902
[libre-riscv-dev] teaching the benefits of using nmigen over VHDL/Verilog
e4/195baa9a7d3fa591132421301530e4ddf679f6 [new file with mode: 0644]