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(parent: e5a30a1) | patch
XICS interrupt controller
authorMichael Neuling <mikey@neuling.org>
Thu, 23 Apr 2020 04:36:05 +0000 (14:36 +1000)
committerMichael Neuling <mikey@neuling.org>
Thu, 23 Apr 2020 06:36:49 +0000 (16:36 +1000)
commitb4f20c20b9a5371ca5f7c8973f756c8908cd65a6
tree19c3e5d60391779d3cecd5bb410862d945605ad0tree
parente5a30a1358f9a7f09c36f54425749c278cfb87e5commit | diff
XICS interrupt controller

New unified ICP and ICS XICS compliant interrupt controller.
Configurable number of hardware sources.

Fixed hardware source number based on hardware line taken. All
hardware interrupts are a fixed priority. Level interrupts supported
only.

Hardwired to 0xc0004000 in SOC (UART is kept at 0xc0002000).

Signed-off-by: Michael Neuling <mikey@neuling.org>
Makefile diff | blob | history
common.vhdl diff | blob | history
core.vhdl diff | blob | history
execute1.vhdl diff | blob | history
soc.vhdl diff | blob | history
xics.vhdl [new file with mode: 0644] blob