allow DDR3 reset (rst) signal to be controlled by DFI commands,
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 25 Feb 2022 01:21:42 +0000 (01:21 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 25 Feb 2022 01:21:42 +0000 (01:21 +0000)
commitb5553cc55a60c36c1068e0b90f0ad2065d0a495e
tree999cae836e5cff5bfd61ae09ffad5f32e43449ef
parent391fdaafbfe94d0c81de6a29955cc3b161316f24
allow DDR3 reset (rst) signal to be controlled by DFI commands,
update icarus simulation to match, and
rename dfi.Interface reset signal to reset_n
gram/core/multiplexer.py
gram/dfii.py
gram/phy/dfi.py
gram/phy/ecp5ddrphy.py
gram/simulation/icarusecpix5platform.py
gram/simulation/simsoc.py
gram/simulation/simsoctb.v
gram/test/test_dfii.py