Added support for verilog === operator
authorClifford Wolf <clifford@clifford.at>
Tue, 7 May 2013 12:35:40 +0000 (14:35 +0200)
committerClifford Wolf <clifford@clifford.at>
Tue, 7 May 2013 12:35:40 +0000 (14:35 +0200)
commitb56e06d2f518b79481309636c57fa40500d425e8
tree842793a7e04372e72322e5407bda5fc75aa16fe8
parent595db0d7b963f8ce11321efeb87767bc9ee2fc4a
Added support for verilog === operator
frontends/verilog/lexer.l