verilog: fix wildcard port connections leaking memory
authorXiretza <xiretza@xiretza.xyz>
Thu, 18 Mar 2021 09:38:36 +0000 (10:38 +0100)
committerZachary Snow <zachary.j.snow@gmail.com>
Mon, 14 Jun 2021 17:56:51 +0000 (13:56 -0400)
commitb57e47fad8b4ecd5438ee49c618fc8978a4bb058
tree73f6363ebdc0b6683c52ccd5c1a864d76fc42e70
parent62a42c317c41590b654f59851b4730c89bfcd7ae
verilog: fix wildcard port connections leaking memory
frontends/verilog/verilog_parser.y