Merge pull request #1718 from boqwxp/precise_locations
authorClaire Wolf <clifford@clifford.at>
Tue, 3 Mar 2020 16:38:32 +0000 (08:38 -0800)
committerGitHub <noreply@github.com>
Tue, 3 Mar 2020 16:38:32 +0000 (08:38 -0800)
commitb597f85b13b5369398350ef4ef43b7b2521eb140
tree18ea3d52b5927ea1491162458e16cfcfd3280418
parent91892465e1af2bcb5ec348b86ba4e566b040cb12
parentf80fe8dc22ca2b3639b7b0bbff69458addb05432
Merge pull request #1718 from boqwxp/precise_locations

Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
frontends/ast/ast.cc
frontends/ast/ast.h
frontends/ast/genrtlil.cc
frontends/ast/simplify.cc