Add dummy clock generator
authorOlof Kindgren <olof.kindgren@gmail.com>
Fri, 23 Aug 2019 11:17:35 +0000 (13:17 +0200)
committerOlof Kindgren <olof.kindgren@gmail.com>
Fri, 23 Aug 2019 11:17:35 +0000 (13:17 +0200)
commitb5bccc4c13f5df5637011bc5d4f6f58fd9bee9b7
tree511723ae57a28e4de4489e42239dcb4bb5580225
parent37fe8b954cbf46ca5129b3211cfb1c0b26d6d49b
Add dummy clock generator
fpga/clk_gen_bypass.vhd [new file with mode: 0644]