soc/interconnect: add AXILite2CSR bridge
authorJędrzej Boczar <jboczar@antmicro.com>
Tue, 14 Jul 2020 14:28:29 +0000 (16:28 +0200)
committerJędrzej Boczar <jboczar@antmicro.com>
Wed, 15 Jul 2020 08:36:34 +0000 (10:36 +0200)
commitb692b2a3f126a0ae38a40c95ed9153fa77e44bfa
tree696e4fc53c76a9029bce48f4c26e173a4740b332
parent35149c4e808df4db4d38e9f7d4d9c055b745b77e
soc/interconnect: add AXILite2CSR bridge
litex/soc/interconnect/axi.py